Release Name: 8.2.0

Notes:
Version 8.2.0 (2006-10-24)

Summary

This release simplifies configuration of generated tests.

Notice

  • Generated runners now have a SIMULATOR_INCLUDES array, whose entries
    specify places where Verilog source files, needed by the Verilog design,
    reside.

Details

  • Generated Verilog benches now inherit all `include and `define directives
    from the Verilog design in a simpler manner.
  • A generated test no longer requires its Verilog design to reside in the
    same directory.
  • The sample tests have been updated accordingly.




Changes: