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Release Name: 3.1.0

= Version 0.4 (2006-04-28)

== Summary

This release adds simple ways of reading and writing values to VPI handles, adds documentation for the VPI utility layer, and fixes the pipelined ALU example.

== Details

* Simple, consistent ways of reading and writing values to handles have been added to the VPI utility layer. These ways are described in the SWIG::TYPE_p_unsigned_int class' documentation.

* The makefiles now use the +rbconfig+ library to determine the default compiler and linker flags for Ruby.

* A race condition in the pipelined ALU example has been fixed. This example should now run successfully in all Verilog simulators.

* The project wiki has been abandoned in favor of RDoc.

* The project website is now generated by RDoc.

* Tested and developed using:
  * Ruby 1.8.4 and Icarus Verilog 0.8 on i686 GNU/Linux
  * Ruby 1.8.4 and Mentor Modelsim 6.1d on x86_64 GNU/Linux